It is a constant endeavor to find ways of increasing the noise margins in digital circuits. This is particularly so because of the continued down scaling of the proximity of circuit interconnecting wires for VLSI circuits. As the proximity is reduced, the crosstalk between adjacent wires becomes a more severe problem.
Crosstalk is largely due to signal radiation from one wire which is subsequently picked-up by its adjacent neighboring wires. These undesired, often high amplitude, and generally transient signals are noise to the circuits driven by the neighboring wires. Often these picked-up signals are high enough to cause false logical transitions which cause performance malfunctions. Pickup is greatest for wires running parallel to the wire that is radiating the signal. General known techniques of minimizing pickup by using shielded wires and/or running wires at right angles to each other are used wherever possible. However, in VLSI circuits, the high circuit densities and corresponding inter connecting wire densities, do not lend themselves to these techniques. Thus a technique is required to reduce or eliminate the false logical transitions.
The pickup problem is illustrated in FIG. 1 for a driver/receiver circuit 100. FIG. 1 shows wire B 110 running between and adjacent to wire A 108 and wire C 112. Wire B 110 interconnects the output 118 of a driver circuit 104 with the input 124 of a receiving gate 116. Consider the case in which the output 118 of the driver 104 is held at a logical low, `0` or ground. When wire A 108 and/or wire C 112 carry a signal that is switching from a low to a high, waveform 152 and/or waveform 154, wire B 110 picks up a positive going signal transition spike, waveform 156, at the input node 124 of the receiving gate 116. The level of the picked up positive going signal 156 is dependent upon the finite resistance of wire B 110 and the amount of capacitance and inductance coupling wire B 110 has with its adjacent wires carrying a positive going signal. If this picked-up positive going signal 156 has an amplitude sufficient to trigger the receiver 116 to change its logical state, it causes a circuit malfunction. The level that is just sufficient to trigger the receiver 116 is herein referred to as the receiver's 116 positive going threshold. The positive going threshold is defined as the minimum input voltage level that is recognized by the receiver gate as a logical high that causes the receiver gate to switch its output logical state. A high input positive threshold level makes the receiver gate 116 more tolerant to positive going noise. This reduces the possibility of the gate being triggered by noise when its input is at a low.
A similar situation exists in the case in which the output 118 of driver 104 is held at a logical high, `1` or VDD. When wire A 108 and/or wire C 112 carry a signal switching from a high to a low, waveform 162 and/or waveform 164, wire B 110 picks up a negative going signal transition spike waveform 166 at the input node 124 of the receiver 116. The level of the picked up negative going signal 166 is dependent upon the finite resistance of wire B 110, and the amount of capacitive and inductive coupling wire B 110 has with its adjacent wire carrying a negative going signal. If this picked-up negative going signal 166 is of sufficient amplitude to trigger the receiver 116 to change its logical state, it causes a circuit malfunction. The level that is just sufficient to trigger the receiver 116 is herein referred to as the receiver's 116 negative going threshold. The negative going threshold is defined as the maximum input voltage level that is recognized by the receiver gate as a logical low causing the receiver gate to switch its output logical state. A high input negative threshold level makes the receiver gate 116 more tolerant to negative going noise, thereby reducing the possibility of false triggering when its input is at a high.
Generally, a compromise is made in selecting a noise threshold for both the low to high and the high to low transitions. Thus, the threshold is set at an intermediate level to equally satisfy both transition directions. In FET technologies where the low and high levels are at or near the opposite power rails, the most noise tolerant receiver is one that has a threshold of VDD/2. This is achieved by choosing PFET and NFET that have equal strength. FET strength is controlled by the FET's width/length ratio. With a threshold of VDD/2, the receiving gate of FIG. 1 has a noise tolerance of VDD/2.
In order to take full advantage of technology scaling, wires must be spaced very close to each other. This spacing leads to a situation where noise pickup is higher than VDD/2, causing circuit malfunction. Avoiding this by increasing the spacing between wires, reduces the useable wire density which results in increased chip size and cost. A method is required to reduce the effect of noise on circuit performance, even though the circuit wires run in very close proximity. The present invention describes a receiving gate circuit that has an increased tolerance to noise. This allows wires to be spaced closely together without causing any logic circuits to malfunction.